ATM Load Module

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OC-3c/OC-12c Asynchronous Transfer Mode (ATM) Load Module

Product Men

Ixia's ATM load module enables high performance testing of routers and broadband convergence devices such as broadband remote access server (BRAS) systems and DSLAM. As full-line speed IP packets are generated and analyzed at OC-12 and OC-3 speeds, this dual-port ATM load module provides a cost-effective and space-saving multi-port test environment. ATM load modules can also be selectively configured to support SONET packets (POS); This mode of operation is included in the OC-3C/OC-12c SONET packet/SDH load module data table.

through modular PHY, multi-rate and multiple technologies (ATM and POS),Ixia's ATM load module supports multiple physical interfaces, providing very high flexibility in a single module. Since the RISC CPU of each port runs Linux, this module is running IxChariot®Test applications such as IxNetwork and IxScriptMate provide a powerful platform. With a full range of Ethernet, POS and load modules, ATM load modules enable Ixia to provide the industry's most comprehensive test solution.

Specifications:

Ixia's ATM load module enables high performance testing of routers and broadband convergence devices such as broadband remote access server (BRAS) systems and DSLAM. As full-line speed IP packets are generated and analyzed at OC-12 and OC-3 speeds, this dual-port ATM load module provides a cost-effective and space-saving multi-port test environment. ATM load modules can also be selectively configured to support SONET packets (POS); This mode of operation is included in the OC-3C/OC-12c SONET packet/SDH load module data table.

through modular PHY, multi-rate and multiple technologies (ATM and POS),Ixia's ATM load module supports multiple physical interfaces, providing very high flexibility in a single module. Since the RISC CPU of each port runs Linux, this module is running IxChariot®Test applications such as IxNetwork and IxScriptMate provide a powerful platform. With a full range of Ethernet, POS and load modules, ATM load modules enable Ixia to provide the industry's most comprehensive test solution.



Features

Details

Ports Per Load Module2 ports per module, each may be populated with different physical interface options
Signal RateOC-3: 155.52 Mbps
OC-12: 622.08 Mbps
Hot Pluggable Physical InterfaceOC-3/OC-12, STM1/STM4
Connector TypeDual SC with 1310 nm Multi-mode optics or Dual LC using SFP transceiver with 1310 nm multimode or single-mode optics
Processor/Memory (per port)1392 MIPS PowerPC/256 Mbytes
EncapsulationLLC/SNAP per RFC 2684 (1483)
VC Multiplexing per RFC 2684 (1483)
MPLS LLC per RFC 3035
MPLS Null per RFC 3035
Virtual Circuits65,536 VC IDs/4,096 VP IDs generated among 4,096 unique streams
Emulation ModesUNI or NNI per port
ATM FramingAAL5
Transmit Streams4,096 among 15 interleaved transmit engines
Transmit EngineBuilt-in FPGA logic for wire speed packet generation with timestamps, sequence numbers and packet group signatures. Five User Defined Fields (UDFs) with additional engines for VPI, VCI, IP DA, IP SA, MAC DA, and MAC SA
Receive EngineBuilt-in FPGA logic for wire speed packet filtering, capturing, real-time latency for each packet group, data integrity, and sequence checking
Capture Buffer (per port)8 MBytes
SONET StatisticsLink State, Line Speed, Section LOS, Section LOF, Section BIP (B1), Line AIS, Line RDI, Line REI (FEBE), Line BIP (B2), Path AIS, Path RDI, Path REI (FEBE), Path BIP (B3), Path LOP, Path PLM (C2), Loss of Cell Delineation (LOC)
ATM Transmit StatisticsCells Sent, AAL5 Bytes Sent, AAL5 Frames Sent, Scheduled Cells Sent, Scheduled Frames Sent, Transmit Throughput, Bits Sent
ATM Receive StatisticsCells Received, AAL5 Bytes Received, AAL5 Frames Received, AAL5 CRC Errored Frames, AAL5 Length Errored Frames, AAL5 Timeout Errored Frames, Correctable HCS Errors, Uncorrectable HCS Errors, Idle Cells Received, Bits Received
TCP/IP StatisticsIP Packets Received, IP Checksum Errors, UDP Packets Received, UDP Checksum Errors, TCP Packets Received, TCP Checksum Errors


Flexible Packet

Generation Traffic is generated in real-time by intelligent logic implemented in FPGAs on each Ixia port, and frame parameters are user configurable:

  • ATM VPI/VCI using 12-bit programmable data generators (UDFs) for VPI, 16-bit for VCI

  • Ethernet MAC DA and SA using 48-Bit UDFs

  • Five 32-Bit UDFs can be inserted anywhere in the frame

  • IP header contents, including incrementing, decrementing, or random IP addresses; IP checksums are generated on the fly in hardware

  • Fixed and algorithmic data patterns

  • Correct and erroneous IP checksums

  • AAL5 frame generation with good or bad CRC

Real-Time Latency

Packets representing different types of traffic profiles can be associated with Packet Group Identifiers (PGIDs). The receiving port measures the minimum, maximum, and average latency in real time, for each packet belonging to different groups. Measurable latencies include Instantaneous Latency, where each packet is associated with one group ID only, and Latency Over Time where multiple PGIDs can be placed in "time buckets" with fixed durations. 64K PGIDs are available per port.


Transmit Scheduler

The packet streams transmit engine can generate multiple streams in sequence, each containing multiple packets with custom characteristics. After all packets in the first stream are transmitted, control is passed to the next defined stream in the sequence. After the last stream in the sequence is reached, transmission may either cease or control may be passed on to any other stream in the sequence. Therefore, multiple streams are cycled through representing different traffic profiles to simulate real world traffic.


Extensive Statistics

Each port accumulates ATM, IP, and SONET statistics in real-time. Both transmit and receive statistics can be viewed on a per-port or per-VC basis. Eight Quality of Service counters are available that enable IP TOS measurements. The user can also define two custom statistics dependent upon source and destination IP addresses, data pattern contents, or error conditions.


Data Capture

A comprehensive set of triggers and filters are available based on VPI/VCI, source and/or destination MAC and/or IP addresses, data pattern, and error conditions. Decodes are available for ICMP, IGMP, IP, TCP, UDP, DHCP, MPLS, OSPF, RIP, ARP, and IPX.


Routing Protocols

The ATM Load Module supports all Ixia Routing Protocol Suites, including BGP-4, OSPF, IS-IS, RIP, LDP, RSVP-TE, PIM-SM, MLD, and IGMP. Protocol emulation operates on a local RISC processor running Linux on each ATM test port. This delivers a highly scalable protocol emulation system that becomes more powerful as ports are added.