| Feature | Dual-Speed, 40/100GE Accelerated Performance | Dual-Speed, 40/100GE Reduced Performance |
| Model name | LavaAP40/100GE2P | LavaAP40/100GE2RP |
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| Chassis slots per module | 1 |
| Maximum ports per chassis | |
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| Transceiver support | |
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| CFP interface adapters | |
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| Hardware capture buffer per port | 1.4GB |
| Interface protocols | |
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| Layer 2/3 routing protocol emulation | Comprehensive coverage of routing, MPLS, VPLS, high-availability, IP multicast, switching, Data Center/SDN, Carrier Ethernet, and authentication.
| Comprehensive coverage of routing, MPLS, VPLS, high-availability, IP multicast, switching, Data Center/SDN, Carrier Ethernet, and authentication.
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Host/client protocol support: ARP, NDP, ICMP (PING), IPv4, and IPv6.
| Host/client protocol support: ARP, NDP, ICMP (PING), IPv4, and IPv6.
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| Layer 4-7 application traffic testing | Yes, with IxLoad and the AppLibrary for IxNetwork | No |
| Transmit flows per port (sequential values) | Billions |
| Transmit flows per port (arbitrary values) | 1 million |
| Trackable receive flows per port | 1 million |
| Stream definitions per port | 512 In packet stream (sequential) or advanced stream (interleaved) mode, each stream definition can generate millions of unique traffic flows |
| Table UDF entries | 512K Comprehensive packet editing function for emulating large numbers of sophisticated flows. Entries of up to 256 bytes, using lists of values, can be specified and placed at designated offsets within a stream. Each list consists of an offset, a size, and a list of values in a table format. |
| Packet flow statistics | Track over 1 million flows |
| Transmit engine | Wire-speed packet generation with timestamps, sequence numbers, data integrity signature, and packet group signatures |
| Receive engine | Wire-speed packet filtering, capturing, real-time latency and inter-arrival time for each packet group, data integrity, and sequence checking |
| User defined field features | Fixed, increment or decrement by user-defined step, value list, cascade, random, and chained |
| Filters | 48-bit source/destination address, 2x128-bit user-definable pattern and offset, frame length range, CRC error, data integrity error, sequence checking error (small, big, reverse) |
| Statistics and rates (counter size: 64 bits) | Link state, line speed, frames sent, valid frames received, bytes sent/received, fragments, undersize, oversize, CRC errors, VLAN tagged frames, 6 user-defined stats, capture trigger (UDS 3), capture filter (UDS 4), user-defined stat 5, user-defined stat 6, 8 QoS counters, data integrity frames, data integrity errors, sequence checking frames, sequence checking errors, ARP, and ping requests and replies |
| Error generation | CRC (good/bad/none), undersize, oversize |
| Latency measurement resolution | 2.5 nanoseconds and is compatible with all of Ixia's 10GbE, 1GbE fiber, and 10/100/1000Mbps Ethernet, ATM, and Packet over SONET load modules |
| Latency self-calibration | Ability to remove inherent latency from 40/100GE port electronics when used with MSA or SFF-8436-compliant transceivers |
| MDIO | MDIO v1.4 support is provided for CFP MSA-compliant transceivers |
| Transmit line clock adjustment | Ability to adjust the parts per million line frequency over a range |
| -100 ppm to 100 ppm |
| Layer 1 BERT capability | The load module supports the following BERT features on both 40GE and 100GE speeds: |
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Wide range of statistics, including: Pattern Lock, Pattern Transmitted, Pattern Received, Total Number of Bits Sent and Received, Total Number of Errors Sent and Received, Bit Error Ratio (BER), Number of Mismatched 1's and 0's
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| 40/100GE Physical Coding Sublayer (PCS) test features | IEEE 802.3ba-compliant PCS transmit and receive side test capabilities include: |
Per PCS lane, transmit lane mapping - Supports all combination of PCS lane mapping: Default, Increment, Decrement, Random, and Custom.
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Per PCS lane, lane marker, or lane marker and payload error injections - User-selectable ability to inject errors into the PCS Lane Marker and simultaneously into PCS Lane Marker and Payload fields. This includes the ability to inject sync bit errors into the Lane Marker and Payload. User can control the PCS lane, number or errors, period count and manage the repetition of the injected errors.
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Per PCS lane, receive lanes statistics - PCS Sync Header and Lane Marker Lock, Lane Marker mapping, Relative lane deskew up to 52 microseconds for 40GE and 104 microseconds for 100GE, Sync Header and PCS Lane Marker Error counters, indicators for Loss of Synch Header and Lane Marker, BIP8 errors.
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| IPv4, IPv6, UDP, TCP checksum | Hardware checksum generation and verification |
| Frame length controls | Fixed, random, weighted random, or increment by user-defined step, random, weighted random |
| Preamble view | Allows the user to select to view and edit the preamble contents |
| Link fault signaling | Generate local and remote faults with controls for the number of faults and order of faults, plus the ability to select the option to have the transmit port ignore link faults from a remote link partner |
| Operating temperature range | 41°F to 95°F (5°C to 35°C) |
| Load module dimensions | 16.0”(L) x 12.0”(W) x 1.3”(H) |
| 406mm (L) x 305mm (W) x 33mm (H) |
| Weight | Module only: 9.8 lbs.(4.45 kg) |
Shipping: 12.0 lbs.(5.45 kg) |
